Timer peripheral clock configuration

I am currently doing some baremetal development on E51 core of the icicle kit and I am playing a bit with the Timer peripheral but I would like to know, what is the default frequency of the timer peripheral ? Which clock is supplying this IP ?
Also, I would like to know if there is a prescaler to downscale the timer frequency (without affecting other peripherals) ?

Hi @dylad :slight_smile:

If you’re using the default XML provided with the bare metal example you should have a timer clock of 150MHz. The TRM for PF SoC says:

The CPU cores, L2 Cache, and AMBA infrastructure are clocked from the MSS PLL through a set off dividers. During normal operation, the PLL clock is divided by 1 for the CPU cores, by 2 for the L2 Cache and AXI bus, and by 4 for the AHB/APB bus.

The timer is on the APB bus and in the MSS configuration the CPU clock is set to 600MHz and the AHB/APB clock is set to divide by 4 so the timer should have a frequency of 150MHz supplied from the AHB/APB clock.

In terms of a pre-scaler its not there, if you have a look at the register map in MSTIMER_LO you can see all of the available registers. Can you use a larger load value instead of a pre-scaler?

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Yes I’m using all default parameters.

That’s what I thought. I’ll update my driver to compensate the 150MHz clock input.

Thanks for the quick feedback !

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