Hello! I am interested in disabling the caches in the PolarFire SoC. My very high-level understanding is that I can modify the Linux kernel (perhaps through the device tree) in order to achieve this. Has anyone done this task before (either through the Buildroot or Yocto SDK), and if so, can you please advise how the caches may be disabled? Thanks in advance!
Which caches are your referring to? The L1 (ITIM/DTIM) and / or the L2?
The L2 cache is configured at startup by the HSS and not by Linux. The way to modify the L2 configuration is through the MSS conifgurator and XML. You need to update the MSS configuration to allocate all of the cache ways to LIM/Scratchpad but just as a heads up you will always need 1 way dedicated to the cache so it can’t be fully disabled.
In regards to the L1 cache the TRM has some useful info on this, again you need to have 1 cache way no matter what but you could reconfigure the L1 cache on the go by storing to it.
I hope this helps,
Hi again, @hugh.breslin!
Thanks for helping me get started in the right direction! My main focus is on disabling the L2 cache for some research tasks I’m performing, but learning about how to disable both is interesting to me as well! I don’t need L2 to be fully disabled, so leaving 1 way dedicated isn’t a problem for me.
I’ll take a look at the MSS configurator. Are the required XML edits performed through the configurator, or is this a separate step/process?
Hi again indeed!
Ok cool The work flow should be, open up the config file for the MSS, the Linux one is here and modify the L2 configuration based on that. Then once you generate it the configurator will give you an XML file you then import into your bare metal, in the case of the HSS you’re looking at updating this file. Then rebuild your bare metal and the changes are applied when you run it, for the HSS you need to program it to the eNVM.
Great, thank you! Up to this point, I’ve been working with the factory/reference HSS and using the Buildroot Linux image workflow; I’m assuming that once I rebuild the HSS and program it to the eNVM, I can use the same Buildroot workflow I’m used to? Apologies for all the questions, a lot of this is brand new to me!
No problem Yup you can use the same workflow - the only thing I have no idea on is the performance impact of removing all but one cache way on Linux! It’d be interesting to see how much (or little) this impacts the performance of Linux
I have a follow-up question, is there any way to verify on-device that my changes made their way to the board? Linux seems oddly the same even with disabled L2, so I’m assuming I did something wrong with my procedure (outlined below).
I was able to install Libero SoC and the MSS configurator, and I downloaded the Icicle Kit reference design from Github. Using the MSS configurator, I edited MPFS_ICICLE_MSS_linux.cfg and generated a new component (in a separate working folder). Then, using Libero SoC, I imported the generated ICICLE_MSS.cxz file. From there, I used the “Run Program Action” workflow and programmed the board.
I’m making progress let me know what you think!
you technically could, theres a
way enable register you could read, its done in the MPFS HAL.
I think I know whats going on though - the updated Libero component you created doesn’t actually configure the scratchpad, thats all done by the Hart Software Services on power on. When you generated the MSS component and got the
.cxz file you should also have gotten a
.xml file, this file contains the L2 configuration settings. You need to import that XML into the HSS and overwrite the default XML in this folder. Then program the HSS to eNVM either by adding it as a boot mode 1 client in your Libero design or use the included External Tool configuration in SoftConsole
Thanks for the additional info! I figured it would be easier for me to just work with the HSS in SoftConsole rather than rebuilding/uploading the entire Libero project. I was able to get the HSS built and uploaded to the board via SoftConsole using non-secure boot mode 1, but after connecting to the serial ports on the board, it doesn’t seem to want to boot.
I believe I followed all the necessary steps. Using the HSS source code downloaded from Github, I made a new workspace in SoftConsole and imported the existing project, copied the
def_config file (in the
mpfs_icicle_kit_es folder) to the top-level directory and renamed it
.config, and I also replaced the
ICICLE_MSS_mss_cfg.xml file in boards → mpfs-icicle-kit-es → soc_fpga_design → xml (using the same filename). After all this, the HSS built with no errors in SoftConsole and the eNVM was programmed successfully.
I assumed I did something wrong with my L2 cache disable, so I tried again but I just used the stock
.xml file. However, the board will not boot with that either.
Any ideas for what I may have done incorrectly?
no unfortunately not your steps sound correct, its odd that it wouldn’t come up with the included XML.
Can I check the following:
- if you build with an unmodified version of the HSS (i.e just build the source directly from GitHub) it doesn’t boot? I know you said you reverted the changes its just really odd that wouldn’t come up, what was the version of the HSS / design you were using originally?
- You could try adding the hss-bm1-p0.hex asset from the latest release to your Libero project, this is a tested and working build of the latest HSS, at least with this things should come up for you I know its not exactly what you want but at least it will get you back to a good configuration.
- You could try adding your custom XML to a bare metal project. The MMUART example is usually a good starting place to test bring up.
- You can also debug the HSS, we have a guide on GitHub
I went back to a “clean slate” configuration by uploading the Icicle Kit reference design to the board.
Building and uploading an unmodified version of the HSS worked perfectly! The HSS decompressed from eNVM to L2 Scratch and everything went smoothly from there, including booting to Linux from the SD card.
I think I may know what I did wrong. I believe I may have accidentally adjusted the Scratchpad ways in the L2 Cache section of the MSS Configurator as I was trying to disable just the L2 cache. Now that I know the HSS build/upload works, I can test any adjustments I make! Thanks again for all your help!